In one previous architecture, fast paths in a Generic Logic Block (GLB) in a product term based CPLD were identified by the term "PT Bypass" (see the 1000, 2000, and 3000 families of CPLDs available commercially from Lattice Semiconductor Corporation, Hillsboro, Oregon). The same scheme was used in all three families, and is shown in their 1994 data book (pp. 2-12, 2-13, 2-14, 2-21, 2-26, and 2-32).
The figure on page 2-12 of the data book shows the number and allocation of product terms in the GLB. The figures on page 2-13 show how the fast path is implemented and how the XOR gate can be used. The figure on page 2-14 provides an example of another configuration of the GLB where the second of the four macrocells uses a fast path. A timing model is shown on page 2-21 of the data book indicating that the "4 PT Bypass" is the fastest path through a portion of the GLB. The figures on page 2-26 and page 2-32 indicate that the same scheme has been propagated to the 2000 and 3000 family architectures.
The disadvantage of the Lattice method is that when the "4 PT Bypass" is used, the capability that was previously available for that macrocell is completely lost. The previous capability includes an XOR gate or an OR gate with up to 20 PTs.